1. Field of the Invention
The present invention relates to a memory device, and more particularly, a charge gain stress test (CGST) circuit for a memory device and a test method using the same.
2. Background of the Related Art
Generally, a CGST circuit tests an inflow of unwanted electrons to a floating gate through a tunnel oxide for memory devices, such as nonvolatile memories including a flash memory. A ground source voltage VSS is applied to the source and drain, e.g., of a flash memory cell and then a voltage (a stress voltage) higher than an operating voltage is applied for a predetermined time to a gate. The high voltage applied to the gate is inversely proportional to the time for applying the stress. Thus, when the voltage is high, the stress time is shorter compared to when the voltage is low, where the stress time is longer.
FIG. 1 illustrates a related CGST circuit for a flash memory. A reference current generating unit 1 generates a reference current Iref, and a sense amp 2 outputs a compare result SOUT by comparing the reference current Iref with a cell current Icell. A flash memory cell 3 includes a floating gate and a source, which is connected with a ground source voltage VSS. A first switch SW1 is controlled by a first control signal READ and selectively connects the drain to the sense amp 2 or the ground source voltage VSS and a second switch SW2 selectively connects the gate of the flash memory 3 to a stress voltage Vpps controlled by the first control signal READ, which is used for the stress application, or a read voltage Vppr used for reading a cell state.
In such a CGST circuit, the first switch SW1 connects the drain of the flash memory cell 3 with the sense amp 2 in accordance with the first control signal READ, and the second switch SW2 connects the gate of the flash memory cell 3 with the read voltage Vppr. The sense amp 2 compares the cell current Icell flowing into the flash memory cell 3 with the reference current Iref to thereby output the compare result SOUT. The output signal SOUT from the sense amp 2 could be xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d depending upon the design of the circuit. For example, when the cell current Icell is greater than the reference current Iref, the sense amp 2 may output xe2x80x9c1xe2x80x9d as the output signal SOUT based on the design of the circuit.
The first switch SW1 controlled by the first control signal READ connects the drain of the flash memory cell 3 to the ground source voltage VSS and the second switch SW2 applies the stress voltage Vpps to the gate of the flash memory cell 3 for thereby applying the stress thereto for a predetermined period of time. After applying the stress for the predetermined period of time, the first switch SW1 connects the drain of the flash memory cell 3 to the sense amp 2, and the second switch SW2 connects the gate of the flash memory cell 3 to the read voltage Vppr.
If the flash memory cell 3 has an inferior characteristic, and thus electric electrons flow excessively into the floating gate due to the stress, the sense amp 2 outputs xe2x80x9c0xe2x80x9d because the cell current Icell is smaller than the reference current Iref If the volume of the electrons flowing into the floating gate is very small, the sense amp 2 outputs xe2x80x9c1xe2x80x9d because the cell current Icell is still greater than the reference current Iref. If the output signal SOUT from the sense amp 2 is xe2x80x9c0xe2x80x9d according to such a CGST test, the cell is determined to be in a weak condition.
If directly testing a unit cell by an external device, it is necessary to consider the size of the voltage applied to gate, drain and source. However, in case of making and operating an array by using a circuit installing cells, the size of the voltage applied to each terminal is limited by characteristics of devices and peripheral circuits. In other words, the characteristics of the peripheral circuit and the devices limit the maximum applicable size of the voltage.
Accordingly, since the time for applying the stress is inversely proportional to the applied voltage, there is a limit to reduce the time for applying the stress. When having a chip constituting the nonvolatile memory cell as the array, since there occurs the limitation to the maximum applicable voltage due to the characteristics of the peripheral circuit and the devices, the stress application time, namely the test time, can not be reduced below a specific time, which results in a longer test time. In addition, since the voltage applied to the stress is considerably higher than the operating voltage in the normal operation, a serious burden is placed upon the peripheral circuit unit.
An object of the present invention is to obviate the problems and disadvantages of the background art and other related art.
Another object of the present invention is to optimize the stress time.
Another object of the present invention is to remove the burden of peripheral circuits during the stress test.
Still another object of the present invention is to allow a maximum size of a voltage used for a stress lower than a voltage applied in a normal operation.
A further object of the present invention is to sufficiently increase an absolute value of an applicable stress voltage by using a reference current.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a circuit for performing a charge gain stress test for a nonvolatile memory which includes a reference current generating unit for generating a reference current, a sense amp for comparing a cell current with the reference current and outputting a compare result, a first switch controlled by a first control signal and thus selectively connecting the sense amp or a first voltage to a drain of a nonvolatile memory cell, a second switch controlled by the first control signal and thus selectively connecting the first voltage or a second voltage to a gate of the nonvolatile memory cell, or controlled by a second control signal and thus selectively connecting the first voltage or a third voltage to the gate of the nonvolatile memory cell, and a third switch controlled by the- second control signal and for thus selectively connecting the first voltage or a fourth voltage to a source of the nonvolatile memory cell.
The present invention can be achieved in whole or in parts by a circuit for performing a charge gain stress test for a nonvolatile memory, comprising a reference current generator that generates a reference current; a comparator that compares a cell current with the reference current and outputting a compare result; a first switch controlled by a first control signal to selectively connect the comparator or a first voltage to a drain of a nonvolatile memory cell; a second switch controlled by the first control signal to selectively connect the first voltage or a second voltage to a gate of the nonvolatile memory cell, or controlled by a second control signal to selectively connect the first voltage or a third voltage to the gate of the nonvolatile memory cell; and a third switch controlled by the second control signal to selectively connect the first voltage or a fourth voltage to a source of the nonvolatile memory cell.
The present invention can be achieved in a whole or in parts by a method of performing a charge gain stress test for a nonvolatile memory, comprising the steps of setting a reference current inputted to a sense amp at a predetermined value; repeating erasing and reading operations; applying a stress voltage for a predetermined time; and evaluating a characteristic of a nonvolatile memory cell.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.